Jobs

Pre/Post-layout constraint development to timing closure

Multi-voltage/Switching aware corner definitions

RC/C model selections based on net-lengths/block sizes/layer stack

SI parameter setting expertise

Handshake with the design team and develop functional/DFT constraints

IP level constraint integration

Abstraction expertise like Hyperscale/ILM/ETM

RC Balancing and scaling analysis of full chip clock

RC Balancing and scaling analysis of critical data paths

DMSA @ full chip and custom scripts for timing fixes

Relevant Experience: 4 years +

Job Description:

• B.Tech./M.Tech. in Electrical, Electronics or Computer Engineering.
• At least 4+ years of direct experience in formal verification.
• Ability to identify the suitable design for FV and analyze its complexity.
• Experience of creating formal test plan and test bench containing list of required checkers.
• Ability to dive deep in the RTL structures to understand the design and debug problems.
• Experience with CDC, LP , Security formal is a plus.
• Experience of at least one industry-wide used formal tools such as JG, VC Formal or Questa Formal.
• Proficient in SV and SVA.
• Perl/python/TCL scripting is a plus.

Job Responsibilities

• Independently drive jasper technology on complex designs
• Drive methodology and solution-oriented discussions with key stake holders
• Partner with sales team to help drive account strategy and campaigns
• Evangelize and drive adoption of new technology across customers
• Produce out-of-the-box solutions to customer problems using either tool capabilities or scripting techniques
• Deploy ML based Solutions to improve verification productivity
• Narrow down complex problems to pointed tool issues for R&D resolution
• Collaborate with worldwide AE teams

Experience: 5-25 Years

Locations : India

Skills Required:

• Signal processing background with DSP, Adaptive Signal Processing, Statistical Signal Processing, Massive / Large Scale MIMO Technologies & MIMO Signal Processing / Space-Time Signal Processing
• Wireless Communication Engineering including Digital, Analog & RF Communications
• Wireless Networking expertise especially in Physical Layer and MAC Layer (Link Layer) (L1 / L2)
• Experience in working in Wireless Design & Testing Laboratories
• Modelling in the MAC Layer in C / C++ / System C & Porting same to Target Processor
• FPGA End-to-End Prototyping
• Resources with Hands-on expertise in MATLAB / C / C++ / System C / RTL / Verilog / VHDL / System Verilog / UVM / Tcl / Python / PERL Scripting

Responsibilities

System & Chip (SOC) Architecture Design
• End to End DSP Design & Implementation Capabilities
• Modeling of Algorithms in Floating Point C / C++ / MATLAB
• Converting Floating Point to Fixed Point Algorithms in C / C++ / MATLAB
• Iterative Modeling of Fixed-Point Algorithms to meet Protocol Requirements &
Targets
• EVM- Error Vector Magnitude.
• SNR Vs. BER (To Achieve Target Bit Error Rate @ Lowest possible Target
Signal to Noise Ratio (SNR), as specified in Protocol / Standard for
• All Channel Conditions
• All Convolutional Code Rates
• All Modulation Schemes
• All Data Rates
• To Develop Golden Reference Model for End-to-End Chip Verification including Pre-
& Post Silicon Validation
• Programming DSP Processor in Assembly / C / C++ to meet Time to market (TTM)
targets & Requirements
• Low Power Design Requirements for devices running on Battery Power
• Desirable: RTL Design Engineering, Architecture Design & RTL Design.

Desired Skills:

• Antennas Engineering, Smart Antennas, Beam Forming & MIMO Technologies
• RF Engineering Expertise in Power Amplifiers, HPA- High Power Amplifiers, LNA-Low
Noise Amplifiers, etc.
• Analog / Mixed Signal Design Engineering (Typically Design of PLL, ADC / DAC etc.)

Experience: 3-15 Years

Locations : Hyderabad, Bangalore

Job Description:

• Strong fundamentals in physical design verification using Calibre tool.
• Perform and debug DRC , LVS , Antenna , DFM , ERC and ESD checks on blocks and top – level design. 
• Strong experience in multi voltage domain and design experience with multi-million instances.
• Experience of working in lower geometries(FinFets) is preferred. Experience is TSMC16nm is a plus.
• Automation of DesignREV using TCL scripting is a must. 
• Familiarity of PnR flows and tools such as Cadence Innovus, Synopsys ICC/ICC2 is must.
• Knowledge and hands on virtuoso experience is must.
• Experience in power gating digital designs is a plus.
• Excellent verbal and written communication skills are required.

Experience: 3-15 Years

Locations : Hyderabad, Bangalore

Job Description:

• Experience with Spice or Fast-spice simulators for functional verification(Spectre/APS/XPS, Finesim, etc)
• Experience in executing fullchip cosim simulations
• Hands-on with SV-UVM verification methodology
• Implementation of Assertions
• Experience with Metric driven verification tools (VManager, IMC, etc)
• Basic understanding of Analog circuits

Experience: 3-15 Years

Locations : Hyderabad, Bangalore

Job Description:

• Good Experience in RTL Codes.
• Should have understanding of SDC and constraints syntax.
• Experience in Synthesis in both Block/SOC Level.
• Good Experience in Logical/Physical/Low power Synthesis
• Good Knowledge on Optimization Techniques to achieve the best Performance/Power/Area of the designs.
• Experience with tools and methodologies for Synthesis – hierarchical synthesis, DFT handling, retiming, clock gating, logic restructuring, optimization.
• Expertise in Synopsys Design Compiler Synthesis – DCT/DCG and/or Cadence RC/Genus.
• Working knowledge of multi power domain designs.
• Good Knowledge on CPF.
• Knowledge on Scan Insertion.
• Good in Timing Concepts.
• Experience in STA/LEC/CLP.
• Knowledge on PTPX.
• Knowledge on Spyglass.
• Knowledge on Functional ECO.
• Experience with Perl/TCL.

Experience: 3-15 Years

Locations : Hyderabad, Bangalore

Job Description:

• Very good understanding of timing concepts
• Should have understanding of SDC and constraints syntax
• Work with the design and implementation teams to develop and qualify timing constraints
• Experience in Timing Analysis both at block level and SoC level
• Experience with Industry Timing signoff tools like Primetime / Tempus is a must
• Experience in DMSA or Tweaker
• Should have understanding of different Timing modes and Corners
• Experience in MMMC
• Work closely with the physical design engineers to resolve implementation related timing issues
• Should be able to plan and track self execution and report result on regular basis systematically
• Should be able to solve timing challenges in Block/SOC by manually closing difficult paths
• Should have a clear understanding of Crosstalk delay/noise, Timing derates, AOCV/POCV concepts and its impact of design closure
• Should have worked on Timing ECO generation in multi-voltage designs
• Experience Timing & Noise Signoff  Closure at block level or Full chip-level on advanced process nodes
• Hands on scripting skills on TCL / Perl

Experience: 3-15 Years

Locations : WFH, Bangalore

Job Description:

• Must haves hands on Experience in more than 1 Emulation projects with Synopsys Zebu/Mentor Veloce/Cadence Palladium
• The Emulation engineer will help bring-up SOC designs on Emulator platform for Pre-silicon validation
• Responsibilities include set-up emulation environment, model building, simulate, create run-time environment and emulator bring up.

Responsibilities :

• Create environment, emulation models to verify and validate RTL
• Experience in Zebu synthesis, compilation and synthesis.
• Verify RTL through simulation simulation and Zebu Emulation flow
• Obtain hw capture and analyze and fix RTL
• Experience with Verilog, System Verilog and UVM Verification
• Port ASIC/IP RTL to Emulation platform
• Implement emulation Test benches,
• Run Software test cases on emulator and enable different debug options
• Experience with PCIe4 , USB3 DDR4
• Experience with Speed Bridge Integration and perform real time testing.
• Work closely with the Verification/SW teams.
• Perl/Python scripting is a plus

Experience: 3-15 Years

Locations : WFH, Bangalore, Malaysia, Singapore, Europe Note: Also USA only if you have Visa

Job Description:

• Should be  able to develop the entire unit/sub-system level test bench in SV using UVM from scratch.
• Experience in SV, UVM, and Own  ASIC verification of IP/Subsystem for complex designs in RTL.
• Interact with the Performance verification teams to augment verification through simulations, new verification techniques.
• Work with the specifications and ensure functional and code coverage of all the RTL code. Expert at Verification – Coverage Driven Test Planning, Architecting
• Environments, Verification Flow
• Expertise in high speed protocols like PCIe4, Ethernet, USB3, MIPI, DDR4, AXI, CXL, NOC, etc.
• Experience developing scripts using Python, Perl and Makefile.
• Computer Architecture – ARM/x86 and knowledge on AMBA Bus protocols is a plus
• Functional coverage, and closure, 2 or more IP Verification projects
• Developing test plans, UVM coding for test bench components
• Maintaining existing UVM test bench components Debugging the failures
• Functional coverage , code coverage planning, development and closure
• Perl/Python/shell scripting is good to have

Experience: 15+Years

Location: PAN India

Skills :

1. Design Verification
2. DFT
3. ASIC RTL
4. Physical Design

Experience: 3-25 Years

Location: Canada

Job Description :

1. Design and DFT knowledge.

2. Knowledge of memory architecture, repair and modern memory structure.

3. Basic MBIST architecture and shared MBIST.

4. POST silicon flow for both scan and MBIST.

Experience: 2-25+ Years

Location: All Over India and Abroad (USA, Canada, UK , Sweden , Germany , Romania ,France, Ireland-Dublin ,Israel ,JAPAN, South Korea, Singapore, Malaysia, China, Taiwan )

Notice Period: 0-90 Days

Roles:

• DV Engineers : Lead/Managers SOC/IP/Business Unit Head/AVP
• RTL Engineers-FPGA/ASIC : Lead/Manager/AVP/VP/Director
• DFT Engineers : Lead/Manager/AVP/VP/Director
• PD/STA Engineers : Senior/Lead/Director/AVP/VP
• Analog/IC Layout Engineers : Senior/Lead/Managers
• Analog/IC circuit Engineers : Senior/Lead/Managers
• IO/Memory Layout Engineers : Senior/Lead/Managers
• Memory Design : Senior/Lead/Managers
• Embedded software-Automotive : Senior/Lead
• Embedded software- Linux Device driver development and BSP
• Post silicon validation : Senior/Lead

Experience: 3-25 Years

Location: USA, Canada, UK , Sweden , Germany , Romania ,France, Ireland-Dublin ,Israel ,JAPAN, South Korea, Singapore, Malaysia, China, Taiwan

Roles

• DV Engineers /Lead/Managers SOC/IP
• ASIC RTL Engineers /Lead/Manager
• DFT Engineers /Lead/Managers

Experience:2+ Years

Location: Pune/Ahmedabad/Bangalore

Job Description:

• 2+ Years of Experience in working with FPGAs (Altera or Xilinx)
• Architecture design for FPGA logics
• Minimum 2 Years of experience on RTL Coding in VHDL or Verilog
• FPGA simulation using Modelsim or other simulation tools
• Testing FPGA on board
• Debugging FPGA issues

Experience: 3-25 Years

Location: PAN India and Abroad (USA, Canada, UK , Sweden , Germany , Romania ,France, Ireland-Dublin ,Israel ,JAPAN, South Korea, Singapore, Malaysia, China, Taiwan )

Job Description1:

• Implementation, vector generation/verification, JTAG, boundary scan and simulation.
• Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus.
• Should have participated in successful tapeouts ofSoC/ASIC chips at 40nm or below and achieved test targets.
• Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA.
• Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process
• Excellent problem solving and debugging skills. Proactive in nature
• Leading junior teams, Mentoring/Training and Project leadership.
• Excellent Customer interaction, Communication and Team work skills

Job Description2:

• Has worked on scan-stitching; and has good knowledge of scan-stitching related concepts..
• Has worked on MBISTBISR implementation and is confident with the Tessent flow of mbist-insertion..
• Has worked on ATPG; and is well conversed with the files required to run ATPG.. Knowledge experience with Tessent ATPG (mentor) is a plus
• Has worked on Spyglass-Lint.
• Knowledge on automation scripts is a plus..
• Knows the basics of JTAG & IJTAG.
• Support Spyglass debug and coverage co-relation.
• Support scan-stitching runs.. Debug DRC other scan-related issues
• Support ATPG.. debug ATPG issues.. debug coverage holes.
• Support MBISTBISR insertion.. debug insertion issues verification issues.
• Support gate-level simulations.