Jobs

Experience: 3+ Years

Location: Bangalore/Hyderabad

Job Description:

Implementation : Synthesis , CDC (clock domain crossing ) concepts and analysis , Industry standard tools like Design compiler, Meridian cdc, etc , Familiarity with netlist verification – CLP (low power checks), design checks , linting checks etc.

STA : Good timing concepts, Good understanding of Prime time tool, Ability to understand timing reports , analyze and identify timing bottlenecks, exposure in timing closure flow

Principal Engineers/Sr Design Lead/ Manager : – P&R

Job Description: Looking for suitable engineers with 8 – 10+ years of experience in SOC, Block Level P&R activities

• Must have worked in at least 2 to 3 Full Chip tape outs.
• Must be hands-on technical expert.
• Experience in deep sub-micron designs (65/45/40/28/14/10nm) and associated issues (performance, power, signal integrity, physical verification, manufacturability, scaling)
• Experience in leading SOC, Block Level timing closure and physical design tasks with deep technical knowledge in all  stages of the design (IO Pad-ring,  Power Planning, floor planning,
• placement,  CTS, Routing, noise reduction/crosstalk, extraction, IR drop,
• LVS/DRC and other physical and electrical checks)
• Experience in Low power and high-performance designs.
• Be able and willing to mentor junior team members.
• Should be able to comprehend architecture, architectural limitations from Physical Design perspective, schedule, and volume of the task and personnel requirement.
•  Strong debug skills and Automation savvy.
• Expertise in  Synopsys Tools :
• CC2, PT, StarXT, ICV, Formality

Experience: 2-20 Years

Location: PAN India

Job Description:

• 7nm/5nm experience
• 2 to 8 years of solid PD experience
• Handle blocks 3M to 5M instances complexity Netlist2GDS
• Handle blocks with analog IPs
• Skills for manual/custom placement and routing challenges
• Good abilities for custom clock tree synthesis
• For one project we need familiarity with Synopsys EDA Suites ( Fusion Compiler / StarRC / PrimeTime / PrimeECO )
• For another project we need expertise with Innovus/QRC
• Need to be familiar with Calibre tool for PV

Experience: 3+ Years

Location: Bangalore

Job Description:

• Min 3 and 10 +  years of Layout Design Knowledge in CMOS lower process nodes ranging from 65nm to 3nm.
• Must have experience which includes one or more of Analog/SERDES IPs such as ADC/DAC/PLL/DLL/Thermal Sensor/HBM/DDR/LDO/GPIO/USB/LVDS/MIPI/PCIe
• Must have worked in Intel with Intel flow experience.
• The candidate should have strong layout design concepts starting from bump plan, floor planning, power grid design, FIN FET layouts, Analog layout matching, LVS and DRC clean up, EMIR clean up.
• Hands on Experience in Floor Planning, Placement and routing of blocks and integration of IO’s
• Expertise in handling ESD, LUP, Antenna and analyzing/fixing EMIR issues
• Expertise in Physical Verification checks (DRC, LVS, DFM , Antenna, Latchup Checks & PERC)
• Experience with Std EDA tools, Cadence tool, and physical verification tools
• The candidate needs to have strong communication skills to allow teamwork and problem solving
• Good understanding of Layout Dependent Effects and implementation in layout
• Capable of working independently and with team and coordinating with designers
• Scripting skills with Perl and Cadence SKILL is a plus.

Experience: 3+ Years

Location: Bangalore

Job Description:

• Hands-on Layout Experience in IO/Analog Design including GPIO’s, XTAL  and Special IO’s like LVDS, DDR, DDR2/3, SSTL and USB etc 
• Hands on Experience in Floor Planning, Placement and routing of blocks and integration of IO’s  
• Expertise in handling ESD, LUP, Antenna and analyzing/fixing EMIR issues 
• Expertise in working on CMOS and FinFet layouts in lower nodes (preferably 28nm and below) 
• Expertise in Physical Verification checks (DRC, LVS, DFM , Antenna, Latchup Checks & PERC) 
• experience with Std EDA tools, Cadence tool, and physical verification tools 
• Good understanding of Layout Dependent Effects and implementation in layout  
• Capable of working independently and with team and coordinating with designers 
• Scripting skills with Perl and Cadence SKILL is a plus 

Experience: 3-20 Years

Location: Bangalore

Job Description:

• Min 3 and 10 + years of Circuit Design Knowledge in CMOS lower process nodes ranging from 65nm to 3nm.
• Hands-on experience in Basic Building Blocks Circuit Design of Analog such as Bandgap Reference. Current Mirrors, Sample/Hold, Comparator, Differential Amplifier, Opamp, Bias Generator
• Must have work experience in one or more of Analog/SERDES IPs such as ADC/DAC/PLL/DLL/Thermal Sensor/HBM/DDR/LDO/GPIO/USB/LVDS/MIPI/PCIe
• Must have worked in Intel with Intel flow experience.
• The candidate needs to have strong communication skills to allow teamwork and problem solving
• Knowledge of associated design domains i.e. Analog layout, .libs, RTL/verilog models and scripting language will be considered as advantage.
• Engage with other team members to establish design requirements and IP specifications. Provide technical support to more junior members of the team.
• Knowledge of semiconductor device physics/process technology and ability to work effectively & efficiently in a team environment.

Experience: 3-25 Years

Location: PAN India and Abroad (USA, Canada, UK , Sweden , Germany , Romania ,France, Ireland-Dublin ,Israel ,JAPAN, South Korea, Singapore, Malaysia, China, Taiwan )

Job Description1:

• Working experience in System Verilog and OVM/UVM methodologies. (UVC creation, integration, SV coverage, SV assertions, SV constraints, UVM sequences etc)
• Should have IP/Sub-System level verification experience.
• Develop verification plan, Build complex test-bench environments and identifying corner case scenarios, exposing Arch/corner case bugs and closing coverage
• Experience with coverage driven verification methodologies.
• Experience with High Speed Interfaces- USB, DP/eDP, PCIE, DSI, CSI,
• Knowledge in AMBA bus protocols  APB, AHB & AXI
• Experience with creating & working with Scalable and Reusable test-bench.
• Must have excellent knowledge of ASIC Verification Flow
• Excellent debug  and problem solving skills ( Should be able to reach to root-cause issues)
• Familiarity with scripting languages likes Perl, Python
• Bug tracking – JIRA/CQ
• Experience on any revision tracking tool – Perforce, SVN, CVS
• Team player, can-do attitude is desirable
• Good communication skills.

Job Description2:

• Good understanding of Arm Based SoCs
  • SoC Bus backbone ( ARM NIC, CCN, Bridges, DRAM memory controllers and cache coherency concepts)
  • SoC bus components like MMU, Quality Enhancer.
  • Good understanding of SoC Power Management and Clock management.
  • Experience in at least ONE of these blocks: Amba, Bus Interconnect, Memory interface ( DRAM and LPDDR4 ), PCIE, Ethernet, CAN, UFS, eMMC , Camera MIPI CSI/DSI, DP, ISP, USB, Security Subsystem including ARM TrustZone, GPU, Audio, Video, ARM CPU and Design For Debug ( DFD), peripherals interfaces – UART, I2C, I2S, SPI, flash memory interfaces verification at sub-system/Full-chip level.
  • Experience with SOC Bus protocols: AMBA Bus interfaces (AXI, AHB, APB) and/or OCP highly desirable.
• Must have excellent knowledge of ASIC Verification Flow
• Experience with current verification methodologies (UVM, OVM, VMM, Specman, …)
• Should have SoC level verification experience. ( Build complex testbench environments and identifying corner case scenarios and exposing Arch/corner case bugs)
• Experience in power aware and Low Power management verification.
• Experience in Performance Verification with Emulators is plus.
• Experience with coverage based verification methodologies.
• Excellent debug skills in both functional ( Should be able to Rootcause the issue)
• Familiarity with scripting languages likes Perl, Phython
• Experience with setting up and running gate level simulations

Experience: 3-25 Years

Location: PAN India and Abroad (USA, Canada, UK , Sweden , Germany , Romania ,France, Ireland-Dublin ,Israel ,JAPAN, South Korea, Singapore, Malaysia, China, Taiwan )

Job Description:

• RTL Design using Verilog
• SOC IP Integration
• Interconnect Protocols: AHB, AXI, APB
• SOC Interfaces: GPIO, SPI, I2C, UART (3+)
• High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+)
• Memory Interfaces: DDR or HBM I/O (10+)
• RTL Quality: Linting, CDC, LEC (3+)
• Tools: Spyglass or Jasper, Synopsys DC
• Technical Documentation: uArchitecture Specification, SoC Integration Specification
• Foundry Porting Experience: Technology Library Conversion