Pre/Post-layout constraint development to timing closure

Multi-voltage/Switching aware corner definitions

RC/C model selections based on net-lengths/block sizes/layer stack

SI parameter setting expertise

Handshake with the design team and develop functional/DFT constraints

IP level constraint integration

Abstraction expertise like Hyperscale/ILM/ETM

RC Balancing and scaling analysis of full chip clock

RC Balancing and scaling analysis of critical data paths

DMSA @ full chip and custom scripts for timing fixes

Relevant Experience: 4 years +