Experience: 3+ Years

Location: Bangalore/Hyderabad

Job Description:

Implementation : Synthesis , CDC (clock domain crossing ) concepts and analysis , Industry standard tools like Design compiler, Meridian cdc, etc , Familiarity with netlist verification – CLP (low power checks), design checks , linting checks etc.

STA : Good timing concepts, Good understanding of Prime time tool, Ability to understand timing reports , analyze and identify timing bottlenecks, exposure in timing closure flow

Principal Engineers/Sr Design Lead/ Manager : – P&R

Job Description: Looking for suitable engineers with 8 – 10+ years of experience in SOC, Block Level P&R activities

• Must have worked in at least 2 to 3 Full Chip tape outs.
• Must be hands-on technical expert.
• Experience in deep sub-micron designs (65/45/40/28/14/10nm) and associated issues (performance, power, signal integrity, physical verification, manufacturability, scaling)
• Experience in leading SOC, Block Level timing closure and physical design tasks with deep technical knowledge in all  stages of the design (IO Pad-ring,  Power Planning, floor planning,
• placement,  CTS, Routing, noise reduction/crosstalk, extraction, IR drop,
• LVS/DRC and other physical and electrical checks)
• Experience in Low power and high-performance designs.
• Be able and willing to mentor junior team members.
• Should be able to comprehend architecture, architectural limitations from Physical Design perspective, schedule, and volume of the task and personnel requirement.
•  Strong debug skills and Automation savvy.
• Expertise in  Synopsys Tools :
• CC2, PT, StarXT, ICV, Formality