Experience: 3-15 Years

Locations : Hyderabad, Bangalore

Job Description:

• Good Experience in RTL Codes.
• Should have understanding of SDC and constraints syntax.
• Experience in Synthesis in both Block/SOC Level.
• Good Experience in Logical/Physical/Low power Synthesis
• Good Knowledge on Optimization Techniques to achieve the best Performance/Power/Area of the designs.
• Experience with tools and methodologies for Synthesis – hierarchical synthesis, DFT handling, retiming, clock gating, logic restructuring, optimization.
• Expertise in Synopsys Design Compiler Synthesis – DCT/DCG and/or Cadence RC/Genus.
• Working knowledge of multi power domain designs.
• Good Knowledge on CPF.
• Knowledge on Scan Insertion.
• Good in Timing Concepts.
• Experience in STA/LEC/CLP.
• Knowledge on PTPX.
• Knowledge on Spyglass.
• Knowledge on Functional ECO.
• Experience with Perl/TCL.