Experience: 3-15 Years

Locations : Hyderabad, Bangalore

Job Description:

• Strong fundamentals in physical design verification using Calibre tool.
• Perform and debug DRC , LVS , Antenna , DFM , ERC and ESD checks on blocks and top – level design. 
• Strong experience in multi voltage domain and design experience with multi-million instances.
• Experience of working in lower geometries(FinFets) is preferred. Experience is TSMC16nm is a plus.
• Automation of DesignREV using TCL scripting is a must. 
• Familiarity of PnR flows and tools such as Cadence Innovus, Synopsys ICC/ICC2 is must.
• Knowledge and hands on virtuoso experience is must.
• Experience in power gating digital designs is a plus.
• Excellent verbal and written communication skills are required.