ASIC RTL Design Engineer
NarendraJobs
Full Time
Asia, Canada, China, Europe, France, Germany, Ireland, Israel, Japan, Malaysia, PAN India, Romania, Singapore, South Korea, Sweden, Taiwan, UK, USA
Posted 3 years ago
Experience: 3-25 Years
Location: PAN India and Abroad (USA, Canada, UK , Sweden , Germany , Romania ,France, Ireland-Dublin ,Israel ,JAPAN, South Korea, Singapore, Malaysia, China, Taiwan )
Job Description:
- RTL Design using Verilog
- SOC IP Integration
- Interconnect Protocols: AHB, AXI, APB
- SOC Interfaces: GPIO, SPI, I2C, UART (3+)
- High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+)
- Memory Interfaces: DDR or HBM I/O (10+)
- RTL Quality: Linting, CDC, LEC (3+)
- Tools: Spyglass or Jasper, Synopsys DC
- Technical Documentation: uArchitecture Specification, SoC Integration Specification
- Foundry Porting Experience: Technology Library Conversion