Experience: 3+ Years

Location: Bangalore

Job Description:

• Min 3 and 10 +  years of Layout Design Knowledge in CMOS lower process nodes ranging from 65nm to 3nm.
• Must have experience which includes one or more of Analog/SERDES IPs such as ADC/DAC/PLL/DLL/Thermal Sensor/HBM/DDR/LDO/GPIO/USB/LVDS/MIPI/PCIe
• Must have worked in Intel with Intel flow experience.
• The candidate should have strong layout design concepts starting from bump plan, floor planning, power grid design, FIN FET layouts, Analog layout matching, LVS and DRC clean up, EMIR clean up.
• Hands on Experience in Floor Planning, Placement and routing of blocks and integration of IO’s
• Expertise in handling ESD, LUP, Antenna and analyzing/fixing EMIR issues
• Expertise in Physical Verification checks (DRC, LVS, DFM , Antenna, Latchup Checks & PERC)
• Experience with Std EDA tools, Cadence tool, and physical verification tools
• The candidate needs to have strong communication skills to allow teamwork and problem solving
• Good understanding of Layout Dependent Effects and implementation in layout
• Capable of working independently and with team and coordinating with designers
• Scripting skills with Perl and Cadence SKILL is a plus.