Experience: 5-25 Years

Locations : India

Skills Required:

• Signal processing background with DSP, Adaptive Signal Processing, Statistical Signal Processing, Massive / Large Scale MIMO Technologies & MIMO Signal Processing / Space-Time Signal Processing
• Wireless Communication Engineering including Digital, Analog & RF Communications
• Wireless Networking expertise especially in Physical Layer and MAC Layer (Link Layer) (L1 / L2)
• Experience in working in Wireless Design & Testing Laboratories
• Modelling in the MAC Layer in C / C++ / System C & Porting same to Target Processor
• FPGA End-to-End Prototyping
• Resources with Hands-on expertise in MATLAB / C / C++ / System C / RTL / Verilog / VHDL / System Verilog / UVM / Tcl / Python / PERL Scripting

Responsibilities

System & Chip (SOC) Architecture Design
• End to End DSP Design & Implementation Capabilities
• Modeling of Algorithms in Floating Point C / C++ / MATLAB
• Converting Floating Point to Fixed Point Algorithms in C / C++ / MATLAB
• Iterative Modeling of Fixed-Point Algorithms to meet Protocol Requirements &
Targets
• EVM- Error Vector Magnitude.
• SNR Vs. BER (To Achieve Target Bit Error Rate @ Lowest possible Target
Signal to Noise Ratio (SNR), as specified in Protocol / Standard for
• All Channel Conditions
• All Convolutional Code Rates
• All Modulation Schemes
• All Data Rates
• To Develop Golden Reference Model for End-to-End Chip Verification including Pre-
& Post Silicon Validation
• Programming DSP Processor in Assembly / C / C++ to meet Time to market (TTM)
targets & Requirements
• Low Power Design Requirements for devices running on Battery Power
• Desirable: RTL Design Engineering, Architecture Design & RTL Design.

Desired Skills:

• Antennas Engineering, Smart Antennas, Beam Forming & MIMO Technologies
• RF Engineering Expertise in Power Amplifiers, HPA- High Power Amplifiers, LNA-Low
Noise Amplifiers, etc.
• Analog / Mixed Signal Design Engineering (Typically Design of PLL, ADC / DAC etc.)